descriptionCollection of VHDL cores
ownerunknown
last changeMon, 26 Feb 2018 16:46:52 +0100
changes
Mon, 26 Feb 2018 16:46:52 +0100 phip Extended the SiFRing decoder by a signal to clear the RX FIFO. default tip
Tue, 23 Jan 2018 12:35:30 +0100 phip Added write to unused signal to avoid a latch when synthesized.
Sat, 13 Jan 2018 12:59:16 +0100 Philipp Burch Fixed SPI master and extended testbench.
Sun, 07 Jan 2018 22:14:16 +0100 phip Extended SPI master testbench to compare the CPHA options.
Sun, 07 Jan 2018 16:37:11 +0100 Philipp Burch Implemented simple SPI master entity. Not fully tested yet.
Tue, 02 Jan 2018 15:38:52 +0100 phip Implemented rxDoneVec vector to report individual changes to registers in the SiFRing register interface.
Tue, 02 Jan 2018 14:14:03 +0100 phip Removed old detector table (not actually used).
Sun, 19 Nov 2017 22:09:47 +0100 phip Implemented IRQ output for I2C master core. Not tested on hardware yet.
Tue, 01 Aug 2017 15:08:17 +0200 phip Fixed SiFRing register interface core to generate at least two full idle cycles after each master TX packet.
Tue, 01 Aug 2017 14:29:38 +0200 phip Implemented full-cycle idle sequence in SiFRing encoder to ensure a balanced signal under all circumstances.
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Mon, 26 Feb 2018 16:46:52 +0100 409ea0d657e0 default
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